Model-specific silicon gates

No gate passes without linked evidence.

Gate 0 — workload

Paid demand, representative traces, quality floor, stable bottleneck.

Gate 1 — software ceiling

Best available runtime and GPU optimization still miss the product target.

Gate 2 — architecture

Cycle, memory, power, area, yield, package, and total-system model.

Gate 3 — compiler

Representative model graphs map reliably; unsupported operations and escape hatches are explicit.

Gate 4 — FPGA / emulation

Functional correctness, host I/O, scheduling, observability, and real kernels work end to end.

Gate 5 — customer

Buyer accepts quality, model boundary, deployment shape, price, and delivery risk.

Gate 6 — tapeout

Verification closure, DFT, physical plan, package/board, firmware, manufacturing slots, and capital buffer.

Red-team

• Move to a plausible new attention or MoE architecture.
• Advance the GPU and open-source software baseline to expected ship date.
• Tighten the quality floor.
• Delay manufacturing by two quarters.
• Cut the committed customer volume in half.